The Web Site to Remember National Semiconductor's Series 32000 Family

PLAYER

In January 2014 I got two old Altera development boards for 300 from e-bay. This development board was released in 2007. I don't know the price for a new board since it is no longer sold. But it must be expensive due to the FPGA used: a Stratix II EP2S60F672C3N. This is the fastest speed grade of the Stratix II device family. The board has 32 MByte DRAM, 2 MByte SRAM, 4 MByte Flash, an Ethernet port and many connectors in a formt ideal for hobbiest.

The FPGA is nearly three times bigger than the Cyclone IV on the DE0-nano board. I realized immediately when I read the facts about the board that this could be the ideal system for MP3 decoding. M32632 V1.0 in Cyclone IV E is limited to 35 MHz and can't decode MP3 in real time. But in a Stratix II FPGA M32632 V1.0 is running at 45 MHz. This speed will break the barrier!

But there is a serious drawback with this board. Altera's Stratix FPGAs are generally not supported in the Web edition of the Quartus software. For my MP3 project I got a test license which works for 60 days. This time was sufficient to create an embedded system with a well defined feature set: the PLAYER. But if you design one day this and next month that then working with a test license is no fun.

Some smaller Stratix III FPGAs are supported in the Web edition of Quartus. But you don't find any development boards using them. My second Stratix II board should become the TITAN5 system. I don't think that this job can be finished in 2 months ...

Fig. 1. The PLAYER system serving as an MP3 player for the living room.

The PLAYER decodes MP3 files with 128 kbit/s stored on an SD card. The analog output is generated by a dual 12-bit DAC. For me the sound is surprisingly good despite the low resolution. A 2*20 character LCD display together with 4 buttons are making the user interface. The LCD display has a big format and is readable even from a distant of 3 meters.

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