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This page presents three topics : the top level view of the M32632 CPU, the system level view and the timing level view.

Top Level View

In Figure 1 the symbol of the M32632 CPU can be seen. The symbol is used in Altera's design software when you create a system in which the CPU is a component. The pins on the left side are all input pins and the pins on the right side are all output pins. Normally all of this pins are not directly connected to real I/Os of the FPGA. Inside an FPGA no bidirectional connections exists. Therefore a databus has always two components, one for reading and one for writing.

Fig. 1. The symbol of the M32632 CPU.

I/O signals which belong to a certain function are described in the following tables.

Basic Signals

Signal Dir Function
BCLKINBasic Clock
MCLKINMemory Clock, normally multiple times of BCLK
BRESETINReset synchronized to BCLK
WRCFGINConfiguration of write to DCACHE behavior
DRAMSZ[2..0]INConfiguration of DRAM size
NMI_NINNon maskable interrupt signal
INT_NINMaskable interrupt signal
STATUS[3..0]OUTStatus code for General Purpose Interface
ILOOUTInterlocked bus cycle
STATSIGS[7..0]OUTState signals which can be used to monitor CPU activity

BCLK should be also the system clock. MCLK must be an integer multiple of BCLK. Otherwise asynchronous behavior will occur.

General Purpose Interface

Signal Dir Function
IO_RDOUTRead access
IO_WROUTWrite access
IO_READYINAcknowledge signal for end of access
IO_A[31..0]OUTAccess address
IO_BE[3..0]OUTByte enable signal for write access
IO_DI[31..0]OUTData bus used for writing
IO_Q[31..0]INData bus used for reading

DRAM Interface

Signal Dir Function
IC_ACCOUTInstruction cache read access
IDRAM_ADR[27..0]OUTAddress of instruction cache access
IC_MDONEINAcknowledge signal for end of instruction cache access
IWCTRL[2..0]INInstruction cache write control
DC_WROUTWrite access
DC_ACCOUTData cache read access
DRAM_ADR[27..0]OUTAddress of data cache access
DC_MDONEINAcknowledge signal for end of data cache access
DWCTRL[2..0]INData cache write control
DRAM_DI[35..0]OUTByte enable signal and data for memory write access
DRAM_Q[31..0]INMemory data bus used for writing into the caches
WAMUXINAddress multiplex signal for a cache write access
WADDR[11..2]INWrite address for the caches
ENWRINEnable write signal for the data cache (write buffer empty)
ENDRAMINEnable DRAM after system initialization

The M32632 CPU must be configured to the DRAM size of the system. Currently the CPU can be used with a maximum of 256 MBytes of DRAM memory.

DMA Interface

Signal Dir Function
HOLDINHold request signal
HLDAOUTHold acknowledge signal
DMA_CHKINThe address bus DMA_AA is valid
DMA_AA[27..4]INDMA address which is currently accessed

Coprocessor Interface

Signal Dir Function
COP_GOOUTStart coprocessor operation
COP_OP[23..0]OUTCoprocessor operation code
COP_OUT[127..0]OUTData to coprocessor, two 64 bit quad words
COP_DONEINCoprocessor has finished operation
COP_IN[63..0]INData from coprocessor, one 64 bit quad word

System Level View

Today every simple development board for FPGAs has enough DRAM capacity to build a capable computer system. Figure 2 shows a typical system where most of the functions are integrated in the FPGA. The use of a DMA controller is optional.

Fig. 2. Computer in an FPGA : the world of today.

Timing Level View

The clock signal MCLK is running synchron to the clock signal BCLK. The best way to achieve this behavior is to use one PLL for both signals.

Fig. 3. The clock signals of the M32632 CPU.

Figure 4 shows the timing of basic I/O cycles. A read access (IO_RD="1") needs two clock cycles if an FPGA memory block is accessed. The reason is that the address is latched inside the memory block and data (IO_Q="00000075") is valid after latching the address. If BCLK is slow the falling edge can be used for latching the address and then the access can be done in one clock cycle. A write access (IO_WR="1") inside the FPGA is done in one clock cycle. The high state ("1") of the signal IO_READY tells the CPU that the access can be finished. External accesses normally require multiple clock cycles.

Fig. 4. I/O read and write of the M32632 CPU.

Figure 5 shows a read access of the data cache at the DRAM interface. DC_ACC is set to "1" at the beginning of the DRAM access. Two clock cycles later the signal DC_MDONE is set active ("1"). Its purpose is similar to IO_READY. Now the data is coming in. Each time the signal DWCTRL[1] is active ("1") a 32-bit data word is written in the cache memory. In this system it is active every second clock cycle because the external DRAM is a SDRAM device which can only deliver 16 bits in one clock cycle. WAMUX is active ("1") if data is written and feeds the address WADDR to the cache memory. Please note that WADDR starts at x'0A1 instead of x'0A0. This is the address of the data which the CPU wants to access. Therefore it is written first. DWCTRL[2] is a load signal for the first data word.

Fig. 5. DRAM access to fill the DCACHE of the M32632 CPU.

More informations about the M32632 V1.0 and how to build a system with it can be found in the next two documents:

M32632 Version 2 Architecture

M32632 Version 2 User's Manual

This chapter was last modified on 15 August 2016. Next chapter: Performance